Isolating and Characterizing Critical Traces Using EM Analysis
4 www.cadence.com/go/awr
Integrated AWR AXIEM Solver/Virtuoso RF Flow
The integrated AWR AXIEM EM solver within the Cadence IC/system-in-package (SiP) flow for layout of silicon ICs provides
design optimization and layout verification within a single schematic. Figure 2 shows the golden schematic flow for an
example design of a voltage-controlled oscillator (VCO).
Figure 3: Golden schematic flow
The left side of Figure 2 shows the schematic of the VCO and the right side shows the layout. Traditionally, layout and
schematic are loosely coupled in the Virtuoso environment. The golden schematic couples much more tightly with the layout,
reducing error and saving time. The spiral in the layout has a corresponding model in the schematic, as is shown by the arrow.
Later it will show how the model can be replaced by S-parameter results from the AWR AXIEM software, enabling the layout
and schematic to stay connected.
Figure 3 shows the golden schematic on the left and the AWR AXIEM spiral layout in Virtuoso RF Solution. The model assistant
is docked on the right side of the layout window.
Figure 4: AWR AXIEM model in Virtuoso RF Solution
The white box drawn around the spiral is the limit of the layout that is extracted to AWR AXIEM software, in this case the spiral
and feed lines. Ports are automatically attached to the feed lines once the layout is placed in the AWR AXIEM simulator. There
is no need for the designer to add ports, they are added wherever the feed lines hit the simulation boundary in the Virtuoso
layout. The box on the far right is the model assistant. It enables the designer to set the AWR AXIEM simulator nets and
various control options.
