Isolating and Characterizing Critical Traces Using EM Analysis
2 www.cadence.com/go/awr
Why EM Simulation for Analog Silicon Design?
In the traditional III-V flow for gallium arsenide (GaAs) and gallium nitride (GaN) chips, the nets are included as distributed line
models, and EM simulation is used to check the models and the coupling between elements. In the traditional analog flow for
silicon chips, the nets are treated as parasitics and modeled as lumped elements. EM simulation is useful in silicon for
distributed structures such as inductors and for coupling between elements such as multiple inductors, pads, and bond
wires. Other common cases where EM simulation is needed include modeling ground meshes, ground issues, or frequency
dependent loss in interconnects.
Parasitic effects not included in models become more important in silicon as the frequency of operation gets higher. The
electrical length is longer, coupling is more likely, imperfect ground is more of an issue, and the loss changes with the skin
depth in the metal. Modules and board transitions, as well as bond wires and ball-grid arrays become more of an important
issue.
An important difference between EM simulators and the more traditional parasitic net extraction tools used in RFICs is that, in
EM simulators, ground is an important issue because they need a ground definition for S-parameters. In addition, ports need a
port ground definition in terms of from where the current comes and what the port voltage reference is. Thus, the designer
must have a good awareness of the ground location for an EM simulation.
Figure 1: Processed wafer with integrated passive elements
