Isolating and Characterizing Critical Traces Using EM Analysis
6 www.cadence.com/go/awr
The log file is available to view once the project is completed, shown in Figure 6. The log file enables the designer to obtain useful
information about the simulation such as the mesh size, the number of frequency points required, simulation time, and more.
Figure 7: The AWR AXIEM log file is available to view
The goal of the Virtuoso RF Solution/AWR AXIEM EM solver flow is to enable the designer to stay within Virtuoso RF Solution
environment and yet gain access to S-parameters with full-wave accuracy. After the S-parameters are generated, the model
in the golden schematic is replaced with the S-parameter results. The extracted view is then created, and the model in the
schematic is replaced with the S-parameters. Figure 7 illustrates the control menus for creating the extracted view.
Figure 8: The extracted view is created, replacing the model with the S-parameters
This flow enables the designer to maintain the original layout and golden schematic. Notice in Figure 8 that the pin count and
net names are correct after extraction to the schematic. This is important for checking the circuit, especially when running
LVS, which is required for all silicon designs before the chip can be manufactured in order to ensure the layout and the
schematic represent the same design. Otherwise, the layout could contain errors, such as critical nets that could be shorted,
that might not be noticed by the layout team, resulting in disastrous consequences. The flow keeps the schematic and the
layout synchronized together, thereby not breaking the LVS flow.
Figure 9: Extracted view and golden schematic with AWR AXIEM S-parameters
