AWR Application Notes

EM Verification of Complex Board Structures in the AWR Design Environment Platform 3 www.cadence.com/go/awr The EM setup wizard can also propagate net selection through open gaps in the net where (series) surface-mount compo- nents would be located. For complicated boards with many components, this capability makes net selection much faster than manually trying to select individual common nets that are interconnecting multiple components. The wizard also highlights the areas containing the nets selected for EM simulation. The PCB EM setup wizard can be used to confirm visibility of layers and select the kind of cutout style desired, i.e., details of the PCB area surrounding the selected trace(s). The default is a bounding box, but in this case, to avoid selecting areas that are not of interest, which adds unnec- essary simulation time, the user can specify a bounding polygon. This feature also allows the user to adjust the distance from the selected trace metals to the edges of the bounding box. Next, the simulation space can be trimmed to a reasonable size using the Create EM Clip Region command, which provides different options for the size and shape of the simulation space. These simplification tools provide users with choices, and the wizard looks at the nets and geometries and offers suggestions based on the geometries. Designers can edit the suggestions or accept them all. The premise here is to enable faster EM simulation without compromising accuracy. Add Ports Now that the EM structure exists, ports can be added, and the simulation can be performed. The PCB EM setup wizard assists with this task as well. The pins of interest have already been selected, and rather than repeating, they can be restored in the EM structure through the wizard. Once the simulation is done, it is easy to bring the results into a schematic and wire up components that automatically show up on the subcircuit and schematic. Even better, it is easy to create custom symbols based on the layout of the PCB EM structure so that is easy to visually know what port is where in the layout. In just a minute or two, it is possible to import a PCB design into the AWR Design Environment platform, intelligently trim down the problem to the region of interest, get it ready for EM simulation, hook up the surface-mount components in a schematic, and look at the performance. A simplified diagram of the available design flow for EM verification of PCB layouts from third-party comput- er-aided design (CAD) tools is shown in Figure 3. Figure 3: Design flows for EM verification of PCB layouts from third-party CAD tools For this structure, the resulting mesh is around 20,000 unknowns (Figure 4). With the use of the wizard, the mesh and resulting unknowns are reduced, significantly shortening simulation time so results are obtained more quickly—without losing accuracy. Figure 4: Shape simplification reduces the number of unknowns in the mesh, thereby reducing simulation time

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