AWR Application Notes

EM Verification of Complex Board Structures

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EM Verification of Complex Board Structures in the AWR Design Environment Platform 2 www.cadence.com/go/awr PCB Design Example A Zuken-designed PCB is used as an example to demonstrate how the PCB import wizard works. The board design is imported into AWR ® software using the wizard, and then, in order to streamline the EM analysis/verification process, the parts of the board that do not impact the performance are cut out. Import PCB XML Files The process begins by selecting the file. The wizard imports XML files using the IPC-2581 standard format developed by the ICP-2581 Consortium for PCB and assembly manufacturing description data and transfer methodology. The wizard also supports 3Di and ODB++ formats. Once the file is selected, all layers, nets, and stackup information that are in the PCB file are directly read by the wizard and imported into AWR software. Designers can specify exactly which layers and nets they want to import (Figure 1). By executing the Copy to EM Structure command, the layout is then sent to the EM simulator of choice, in this example the AWR AXIEM ® planar EM simulator within the AWR Design Environment platform. Ports can easily be added to the component pins and pads by selecting Create Ports From PCB Pins. The wizard then runs the information specified by the designer, imports the file, and produces a layout of the entire board, ready for EM simulation. Figure 1: The complete PCB layout (courtesy of Zuken) and the selected region of interest (pop out) for further analysis Select Layer Visibility Options and Net Routes Once the board is imported, layer visibility options can be selected to make it easier to see exactly what is to be simulated (Figure 2). The Select Net Routes command propagates the selection of nets based on the net names, thereby selecting anything that has the same net names, i.e., the entire trace. For complex PCBs, there are many traces running between pins and so the objective is to use EM simulation on only critical nets on the board, thus saving considerable simulation time. This is accomplished by isolating the area of interest from the rest of the layout. Figure 2: Critical traces set for further analysis In this design, some of the pins have nets that connect to different ground or power planes at the port. If this is the case, the user has an alternative method of selecting nets that applies further automated intelligence. The PCB EM setup wizard works similarly to the Select Net Routes command in that it propagates the selection down nets omitting (not select) shapes that are connected to either power or ground nets.

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