AWR White Papers

EDA Software Design Flow Considerations for the RF/Microwave Module Designer

Issue link: https://resources.system-analysis.cadence.com/i/1372768

Contents of this Issue

Navigation

Page 6 of 7

Optimization and Yield Analysis Another challenge within an EDA module design flow is to perform optimization and yield analysis. With AWR Microwave Office software, both the module and MMIC are in the same design, so optimization and verification can be simultaneously performed on the two portions of the design. Values of surface-mount capacitors (SMCs) can be varied, and the trace width of the module can be modified to accommodate manufacturing tolerances simultaneously while viewing the interactions. In this task, the module-level interconnect can largely be ignored, aside from bondwires and bumps. This level of analysis identifies the chip issues that require addressing. While module-level interconnects (considered in the next task) are essential, at this stage they will only tend to exacerbate detrimental performance, which arises fundamentally from the interaction of two ICs designed independently. Addressing that issue here typically requires modification of one or both of the chips and then an appropriate interconnect. In some cases, module-level interconnect design and analysis needs to be considered concurrently with alterations on one or both of the ICs, and this is best handled as a hybrid between Tasks 4 and 5. Task 5 – EM Verification A final challenge in the module design process is verification using EM simulation, which is desirable when the design is near completion to determine if there is coupling between the microstrip or coplanar waveguide transmission lines, among other things. The AWR Design Environment platform enables EM extraction right from the schematic, so in the case of bondwires, for example, a model for them is already integrated within the EDA environment (Figure 7). Additionally, the software empowers design teams to utilize the right EM solver for each of the different subtasks within the spectrum of functions for which EM analysis is used. Circuit extraction can be done early or for large, complex interconnect networks that may just need a go/no-go test. The Cadence AWR AXIEM ® 3D planar EM simulator can be employed for detailed design work and a full 3D FEM simulation can be run with the AWR Analyst tool for the final word in verification. Figure 7: Variety of windows and views in the AWR Design Environment platform The ability to extract specific elements from the design through an extract block element allows users to choose specific components within the schematic layout that they want to simulate. The next time simulation is performed, the software automatically creates an EM structure and links it to the schematic. This saves multiple time-consuming design steps. When changes are made to the module, instead of having to move between the schematic layout and EM, turn it into a black box, and bring it back into to schematic, the simulation is performed in one place and schematic, layout, and EM results are changed simultaneously. EDA Software Design Flow Considerations for the RF/Microwave Module Designer 7 www.cadence.com/go/awr

Articles in this issue

Links on this page

view archives of AWR White Papers - EDA Software Design Flow Considerations for the RF/Microwave Module Designer