AWR Datasheets

Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world's most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications. www.cadence.com © 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. 14639 06/20 DB/SA/DS-MWO-MMIC/PDF MMIC Design with AWR Software Product Strengths Design Management Advanced report/measurement management enables designers to track multiple simulation results simultaneously, manage measurement data sources and parameters from a single location, and create sets of linked reports in a single dashboard display. Simplified power amplifier (PA) measure- ments provide easy plotting of nonlinear measurements such as gain compression or efficiency versus output power, a common method for presenting amplifier performance. Simulation Circuit-based annotations provide immediate simulation feedback for current density and critical voltages, pinpointing reliability issues long before layout. The unified database architecture dynamically links electrical and physical design for in-situ EM verification and manufac- ture-ready layout. The Cadence AWR ® APLAC ® harmonic balance (HB) simulator combines linear and nonlinear frequency-domain simulation with time-domain transient simulation and is renowned for its speed and convergence on even the toughest of problems. It addresses highly nonlinear problems, networks with large active device counts, and MMICs operating under multi-tone conditions. Design for Manufacturing Design for manufacturing (DFM) is inherent in the AWR software platform, providing accurate modeling of process-specific metal traces and on-chip components from foundry-authorized PDKs. Export of GDSII layout files supports the transfer of design information into dedicated manufacturing tools. PDKs developed in collaboration with leading MMIC foundries provide engineers using AWR Design Environment software with schematics, scalable layout parameterized cells (PCells), advanced layout utilities, and connectivity checking/highlighting, as well as accurate EM simulation featuring predefined substrate stackups and preconfigured simulation settings. AWR software customers maximize profitability by reducing design failures. Yield and corner analysis within the software helps designers study statistical variations on circuit performance and optimize manufacturing yields by modifying the nominal values of specified parameters based on known process tolerances. Features Highlights f Powerful design entry with process-specific models and layout PCells f Accurate, fast, and robust HB simulation f PDKs for III-V semiconductor foundries f Automated circuit extraction (ACE) technology for interconnect modeling f Cadence AWR AXIEM ® EM simulator for design verification and parasitic extraction f Cadence AWR Analyst ™ EM simulator for analysis of bumps, bond wires and ribbons f EM Socket for integration with third-party EM tools f ERC, DRC, and LVS supports production-ready GDSII export f System co-simulation for circuit envelope analysis and wireless standards verification Every designer faces a choice during the design cycle: do I believe the simulation results displayed by the software, or not? I trusted the predictions and, thanks to AWR software, the new design worked perfectly. The performance we achieved is unlike any other MMIC ever produced. Christopher Marki, Marki Microwave

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