Issue link: https://resources.system-analysis.cadence.com/i/1355086
Ensuring Accurate Broadband EM Analysis with Allegro PCB Designer
6 www.cadence.com/go/awr
Mesh Complexity and EM Simulation Run Time
The meshed structure (Figure 12) can now be simulated but it will require a significant amount of memory and lengthy run times.
While Allegro PCB Designer provides an elegant method to place via arrays around metal structures, traces, and transmission lines
to improve shielding between nets and traces, this approach is not friendly to EM simulation/verification. Vias are represented as
circular tubes inside of EDA layout software. This representation can present unnecessarily long simulation run times for EM
analysis tools. Thus, the de facto approach for EM software is to approximate a via with a polygon. While the number and shape of
the vias in the design can be reduced manually, a better approach is to invoke "rules" to simplify the layout and speed up the
simulation without sacrificing accuracy.
Step 4: Using Import Rules to Simplify EM Structures
The PCB import wizard that was used to import the IPC-2581-compatible Allegro layout file automatically creates a schematic
that contains a STACKUP option element (Figure 13) with the PCB properties contained within the Allegro cross-section editor.
Figure 13: Cadence layout file — STACKUP option element revealing board properties
The dielectric layer tab shows the thickness and material definition of each layer, while the Materials Defs lists the detailed
material properties that are used in this design.
The rules tab enables the user to specify additional rules that can be applied when the layout is copied to an EM structure
within the AWR Design Environment platform. A few example rules are shown below to provide a quick-reference starting
point for simplifying the EM structure.
RESHAPE_CIRCLE_DIVS