Ensuring Accurate Broadband EM Analysis with Allegro PCB Designer
4 www.cadence.com/go/awr
Step 3: Ready the PCB Layout Data for EM Simulation/Verification
Using the layout editor within the AWR Design Environment platform, the imported file can be reviewed, edited, and prepared
for an EM simulation. It is a best practice to review each layer individually and verify for proper import of all metal and via
structures. An EM simulation structure can now be created either by selecting all of the imported metal structures or a subsection of
the metal structures. In the layout editor, select all metal structures on layer 1 and layer 2, including all vias, and then select Layout –
Copy to EM Structure.
In the new EM structure dialog box, convert the layout data into an EM simulation structure by selecting the desired EM
simulator, for example, AWR AXIEM - Async. Set the initialization options to From StackUp and select the desired PCB stackup,
in this example SUB1 (Figure 7).
Figure 7: New EM Structure dialog box
Next AWR Microwave Office and AXIEM software will attempt to assign ports automatically and provide an overview list of all
possible port connections that were detected (Figure 8).
Figure 8: EM Ports overview list
For this example, all ports except the ports connected to the nets Through and GND will be disabled and the port numbers 3
and 4 will be re-labeled to ports 1 and 2, as shown in Figure 9.
Figure 9: All ports except the ones connected to Through and GND are disabled, ports 3 and 4 are re-labeled to 1 and 2
