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5.3 Amplifier Design Stages 213 5.3.3 Stage 3 - Impedance Matching Once the transistor has been biased, its S-parameters have been measured and the correct stabilisation technique has been employed to make it unconditionally stable, we can proceed to the last stage of amplifier design: Impedance Matching. As we have seen in previous sections, in order to achieve maximum power transfer between a source and a load, the source and load impedances must be the complex conjugate of one another. A transistor is no different! In order to improve its performance we must use an input matching network which ensures maximum power transfer between the signal source impedance and the input impedance of the transistor and an output matching network which ensures maximum power transfer between the output impedance of the transistor and the load. Several techniques may be employed to design such networks, as will be illustrated in the following sections. 5.3.3.1 Unilateral Matching The concept behind unilateral matching is really quite straightforward. We simply assume that the amount of output-input feedback that we get is negligible and hence we treat input and output ports as if they were totally separate and unconnected. In terms of S-parameters this means assuming that our S12 is equal to zero. There are instances when, even with a finite S12 this assumption is valid. There are formulae which allow us to work out the range of error which we might have to take into account if we decide to use this technique when S12 is not zero. These are beyond the scope of this section. Our starting point is our biased and stabilised transistor (Figure 5.3-7) which is characterised by a power gain G0, which may be derived from the S21 parameter. | | Figure 5.3-7 S-parameters and basic gain measurement for a biased transistor Then we may look at the input impedance of the transistor, which may be obtained from the S11 parameter, and design a matching network so as to transform the source impedance into the complex conjugate of the transistors own input impedance. G 0 Transistor + Bias Z 0 Z 0 S 12 S 21 S 11 S 22 Conquer Radio Frequency 213 www.cadence.com/go/awr

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