CHAPTER 4 - Impedance Matching
166
4.2.5 Parallel RLC
Let us now consider a network that comprises of resistive, inductive and capacitive elements
connected in parallel as shown in Figure 4.2-23, Figure 4.2-24 and Figure 4.2-25.
As we have seen in previous cases, we will probably have a phase difference between voltage and
current which is somewhat less than 90ι due to the presence of the resistor. However the voltage
may either lead or lag the current depending on the values of our capacitor and inductor.
The analysis of this type of network is much easier if we use admittances instead of impedances!
In the circuit shown in Figure 4.2-23, the capacitor and inductor values are such that the modulus of
the susceptance of the capacitor
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|
is lower than that of the inductor
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.
The overall
admittance of the L-C parallel is which means that the inductor
dominates and the voltage leads the current (Figure 4.2-23).
Figure 4.2-23 Parallel R-L-C with inductor dominating
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Let us now examine the circuit in Figure 4.2-24.
Figure 4.2-24 Parallel R-L-C with capacitor dominating
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Freq = 1000 MHz
0 0.5 1 1.5 2
Time (ns)
parallel_R_L_C
-1
-0.5
0
0.5
1
-40
-20
0
20
40
p2
p1
Vtime(M_PROBE.VP1,1)[*] (L, V)
parallel_R_L_C
Itime(ACVS.V1,1)[*] (R, mA)
parallel_R_L_C
p1: Freq = 1000 MHz
p2: Freq = 1000 MHz
0 0.5 1 1.5 2
Time (ns)
parallel_R_L_C
-1
-0.5
0
0.5
1
-40
-20
0
20
40
p2
p1
Vtime(M_PROBE.VP1,1)[*] (L, V)
parallel_R_L_C
Itime(ACVS.V1,1)[*] (R, mA)
parallel_R_L_C
p1: Freq = 1000 MHz
p2: Freq = 1000 MHz
Freq = 1000 MHz
V
mA
V
mA
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