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RF Electronics Chapter 10: Operational Amplifiers Page 346 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. Extending the frequency of figure 10.6 down to 50 Hz, shows that for Rp = 120 kΩ, at 50Hz, a 65.4 dB attenuation occurs. A 240 V mains voltage will thus cause a 384 mV pp at the output of the OpAmp. Halving the value of Rp, will also reduce the mains voltage at the output of the circuit of figure 10.5 by close to 6 dB. The values for Rp used above are thus unlikely to cause any intermodulation distortion in the OpAmp. The Sallen Key amplifier stage in figure 10.4 will attenuate this mains voltage further. For a better comparison, the resistor Rg, shown in figure 10.5, is included in the circuit. For the value of Rg is changed, to ensure a -13 dB amplifier gain for all the different values of Rp. The resulting frequency responses are shown in figure 10.7. The corner frequencies shown are in good agreement with the calculated values shown above, except for Rp = 15 kΩ, where the high frequency response is limited by the characteristics of the OpAmp. To demonstrate this, the frequency response obtained from an ideal OpAmp with a 2 pF input capacitance, is included as the magenta curve in figure 10.7. Figure 10.7. Amplifier circuits of figure 10.5 with same gain and Rs2 varied. For the amplifiers shown in figure 10.7, with a 1 V rms PLC frequency input signal and using a 10 MHz noise bandwidth, the Signal to Noise Ratio (SNR) due to the OpAmps and the thermal noise of the resistors can be calculated as shown later in this chapter. For Rp = 15 kΩ the SNR is 47.4 dB, for Rp = 30 kΩ the SNR is 49.6 dB, for Rp = 60 kΩ the SNR is 51.0 dB and for Rp = 120 kΩ the SNR is 51.9 dB. Figure 10.7 shows that the lowest value of Rp has the widest bandwidth, but the noise calculations show that that also has the lowest SNR. The choice of Rp is thus a compromise. Other OpAmp Stages The high input impedance amplifier stage of figure 10.5 involves the most compromises for the design of the circuit in figure 10.4. The final value used for Rp = 68 kΩ, and Rg is not used, resulting in a PLC frequency signal loss of 23.9 dB for the high impedance input stage. It is desired for the circuit of figure 10.4 to be able to handle PLC input signals up to 8 V pp . Having a unity gain (0 dB) for the whole circuit satisfies this requirement. The remaining stages will this need to have a gain of 23.9 dB for Rp = 68 kΩ RF Electronics: Design and Simulation 346 www.cadence.com/go/awr

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