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RF Electronics Chapter 10: Operational Amplifiers Page 344 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. Figure 10.4 shows the circuit diagram of the complete Voltage Sensor. The operational amplifiers A1 and A2 are a high impedance high pass buffer amplifier. The Cs = 15 pF series input capacitor and the 1.068 MΩ = Rs + Rp resistor to ground, form a passive high pass filter, that together with the active Sallen Key filter result in a 6 th order Butterworth high pass frequency response of the whole circuit. Capacitor Cs, together with the potential divider consisting of the Rs = 1 MΩ and Rp = 68 kΩ resistors ensure that the mains voltage does not cause any damage to the OpAmps A1 and A2. For these values, a 240 V rms 50 Hz mains voltage, results in 217 mV pp at the input terminal of the OpAmp, which is quite safe. That potentiometer has a 24 dB voltage reduction at high frequency. This must be made up using gain in the other part of the circuit. Figure 10.4. PLC Frequency Voltage Sensor. The AD8057/8058 OpAmp has a 2 pF input capacitance (to ground) and that with the 68 kΩ resistor at the input pin of the OpAmp causes a 1.33 MHz low pass corner frequency, which is far less than the 20 MHz required upper frequency. Reducing the 68 kΩ resistor will increase the high frequency corner frequency, but reduces the output voltage of the circuit and will result in a higher output noise. For accurate differential input capability, it is important that both OpAmps A1 and A2 are matched as close as possible. This requires a Dual OpAmp package to be used, so that both A1 and A2 are well matched and operate at the same temperature. The THS4211 of table 10.1 has a lower input impedance, but it is only available as a single amplifier and will result in a poorer differential voltage accuracy. High Impedance Input stage The design options for the high impedance input amplifiers in figure 10.4 will now be considered. A suitable circuit is shown in figure 10.5. An input impedance >1 MΩ is required, so that the amplifier does not load the circuit to be measured, Rs = 1 MΩ satisfies that requirement. With a 10V supply voltage. the OpAmp output should be less than 8V pp to prevent distortion. Any mains voltages at the OpAmp output should be much less than 0.8 V pp to prevent that to cause intermodulation distortion with the PLC frequency signals to be measured. Figure 10.5 shows a first order passive high pass filter with a 10 kHz cut off frequency, consisting of CS = 15 pF, Rs = 1 MΩ and Rp = 68 kΩ. A 240 V 50 Hz mains voltage results in 3.42V pp at the junction of CS and Rs, and 217 mV pp at the OpAmp input. A value of Rp = 250 k Ω results in a mains voltage of 0.8 V pp at the output of A1 or A2 in figure 10.4. Rp must thus be kept < 250 k Ω to prevent mains voltage overload. Rs and Rp in parallel with the 2 pF input capacitance of the OpAmp form a low pass filter, limiting the high frequency response of the amplifier. A lower value of Rp results RF Electronics: Design and Simulation 34 4 www.cadence.com/go/awr

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