RF Electronics Chapter 9: Impedance Matching of Power Amplifiers Page 326
2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0.
Figure 9.33. S parameter sub-circuit for determining Z
11
and Z
22
.
For 350 MHz, that results in:
Z
in
= 2.9313 -j17.968 and Z
out
= 4.2667 – j20.314 Eqn. 9.25
NXP's AN721 [5] and AN1526 [6] and equation 9.2 show that the empirical load
resistance for a power transistor at maximum power is:
�
�
��
��
��
���
�
�
��
���
Eqn. 9.2
Assuming a 50V supply, V
sat
, = 0.3 V, for P
out
= 30W, gives R
L
= 41 Ω. Which is much
larger than the small signal output impedance shown in shown in equation 9.25.
This amplifier design example involves three steps. The first step is to independently
design and optimise the input and output impedance matching networks. The schematic
for the matching networks is shown in figure 9.34 and the FET subcircuit is disabled to
prevent interaction between the matching networks due to S
12
and S
21
of the FET. To
allow optimisation of the individual components, the component values are calculated
using the equations shown in figure 9.35, with the constants K1 to K12 as optimisable
multipliers.
Figure 9.34. Initial Amplifier S parameter subcircuit and matching network.
RF Electronics: Design and Simulation
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