Issue link: https://resources.system-analysis.cadence.com/i/1325428
RF Electronics Chapter 7: RF Filters Page 265 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. figure 7.89 includes the coupling between the hairpin filter and the grounded PCB border ring. Comparing the EM simulation of the hairpin only circuit with the EM simulation of the hairpin with the PCB border, allows the effect of the PCB border to be evaluated. The fourth circuit (4_Hairpin EM Box_PCBRing) is the same as the third circuit, except that copper walls are used for the EM structure in STACKUP and a copper top boundary is used 25 mm above the circuit board. That matches a typical mounting of the circuit board in a metal box enclosure. Varying the height of the top boundary above the circuit board will allow the smallest enclosure size to be determined. Note that AXIEM ignores the sidewall boundary conditions, however the PCB border shown on figure 7.83 minimises any fields at the side boundaries, so that there is no practical difference between having no sidewall or a copper sidewall. Figure 7.90. PCB border simulation using grounded extraction ports. The fifth circuit (5_Hairpin EM EPort_PCBRing) uses the layout of the first circuit and places Extraction Ports on the outer edges of the shapes making up the PCB border. This is done by selecting one of the shapes, Selecting Draw Extraction Port and placing the port on the outside edge of the board. Then select the properties of the extraction port by double clicking on it. Use the Explicit Ground Reference dropdown window to set the port to "Connect to lower". That will then earth the shape and show a ground symbol on the layout. Right-click on the shape and select Shape Properties. Enable EM extraction and set the group name to the name of the EM Extraction element on the circuit schematic. This process is repeated for all the shapes. The resulting layout is shown in figure 7.90. It should be noted that circuit 1, 3, 4 and 5 all have exactly the same layout, but that the PCB border is treated different in their simulation. RF Electronics: Design and Simulation 265 www.cadence.com/go/awr