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RF Electronics Chapter 7: RF Filters Page 263 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. in an enclosure, a grounded track, connected with vias to the ground-plane was included in the PCB layout as shown in figure 7.83. EM simulation allows the designer to ensure that the grounded ring around the circuit does not cause any unwanted changes to the circuit's performance, by including an analysis of the coupling between the filter and the grounded ring. To illustrate the process, an EM simulation of the hairpin filter of figure 7.83 is now described. The first step is to ensure that all circuit elements can be EM extracted. Select each element in turn and select Properties Model Options and ensure a "" is placed in the Enable checkbox of the EM EXTRACT Options window. Add the EXTRACT element to the circuit diagram, by selection Draw More Elements Extraction Control Block, or CNTRL-L and place the Extract element on the circuit schematic, as shown in figure 7.88. Figure 7.88. Hairpin filter circuit with EM control elements added. There are several different EM simulators available, as can be seen from the drop-down selection for the simulator in the EXTRACT element. Analyst allows arbitrary 3- dimensional components to be simulated. In this case, a much simpler 3D planar EM analysis is required. The hairpin circuit is fairly complex, as a result AXIEM is used in this example. It is gives good results and is much faster than EMSight. Select AXIEM in the Simulator dropdown box of the EXTRACT control element. Right clicking on EXTRACT shows which circuit elements are included in the extraction, by highlighting them in red. Ensure that all circuit elements are included. From the circuit element catalogue select Substrates STACKUP and add the Stackup element to the circuit diagram and give that a suitable name if required. Add the Stackup circuit element name to EXTRACT using the STACKUP dropdown box in the EXTRACT element. Left click on the STACKUP element and set E r and other the material definitions and other properties to match the substrate and conductors to be used. For the Line Type property, select Initialise to match the Line Type used to the circuit diagram layers. The Line Type of Top Copper and the Material Name Copper, is used in the circuit of figure 7.88. Repeat this process for any other circuits to be simulated at the same time. Initially use the default settings for the EXTRACT element. Since the EM simulation can take a reasonable time, for the initial EM simulation, set the X and Y cell sizes to 1 mm, until the simulation completes without errors after which the cell sizes can be reduced. Reducing cell sizes will increase the accuracy and the time required to complete the simulation. For example, simulation of one of the enclosures used in the RF Electronics: Design and Simulation 263 www.cadence.com/go/awr

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