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RF Electronics Chapter 2: Computer Simulation Page 30 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. in order to obtain an accurate solution. It is possible to do simulations for multiple operating frequencies of the Buck converter. However, that results in overlapping output plots, so single frequencies are best. The next step is to ensure that the length of the simulation is correct. In this example, we want to analyse the transient response and settling of the output voltage. For the maximum load resistance of 60 Ω, the transient response takes 1.5 ms. Corresponding to 150 periods of the 100 kHz pulse generator V_PLS, are required. Since a 48V supply is switched, it is also necessary to increase the Maximum Voltage or Current Change from the default value of 1 to 100 in this APLAC Sim window of figure 2.34(L). Figure 2.34. Circuit Option settings primary (L) and secondary (R) for transient analysis. Normally, the time stepping is varied to ensure accurate results then changes occur. In this simulation that results in ringing when timing is changed by APLAC. To avoid this in APLAC Sim window in Circuit Options, select Show Secondary as shown in figure 2.34(R) and in Transient Analysis Options, for Time Stepping select Fixed. Then set the Time step values in Transient Options. Set the simulation Stop time to 1.5 ms and set step time to 0.01 s or 1e-5 ms. If the step time is set too large, the simulation will not be accurate and the output voltage may decrease as the On time t on (TW) is increased, instead of increasing as t on is increased. If the step time is too small, the simulation will take long to complete. The settings in the project files for figure 2.31-2.40 incorporates these settings. By making variables or elements tuneable, the effect of their variation can easily be investigated. For the calculated ON time of 2.567 µs, the switching delays result in a steady state output voltage for the converter of 11.52 V. The 0.5 V lower than expected voltage is caused by the 0.5 V drop due to the 0.1 Ω resistance of the inductor. Changing the ON time of the pulse generator to 2.67 µs results in a close to 12V output with little overshoot and ripple at the 5A output current, as shown in figure 2.35. If the simulation of a circuit like the one in figure 2.32 fails, it may be possible to complete it by selecting Options Default Circuit options APLAC Sim Show Secondary. Then for the APLAC Simulation Options AC Options or DC Options, change the settings for the Matrix Solver from Auto Select to one of the other settings like Aplac Sparse. Other changes like reducing the step-time, may also assist in the completion. RF Electronics: Design and Simulation 30 www.cadence.com/go/awr

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