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RF Electronics Chapter 9: Impedance Matching of Power Amplifiers Page 328 2022, C. J. Kikkert, James Cook University, ISBN 978-0-6486803-9-0. Figure 9.35 shows the equations for AWR DE to calculate these matching circuit component values using the manufacturers S parameters as a starting point. The initial component values for the input and output matching networks are calculated at 350 MHz, using a progressive impedance transformation and a lowpass T section at the amplifier terminals and a Pi section at the input and output terminals. These networks are then connected as shown in figure 9.34. The resulting S 11 and S 22 frequency response is shown in figure 9.36. It can be seen that this simple matching procedure provides a reasonable input and output match at 350 MHz, but the matching network parameters need to be optimised to provide a good match over the 300 to 400 MHz band. Performing an optimisation of the constants K1 to K12 results of figure 9.34 results in the frequency response shown in figure 9.37. Figure 9.37. Optimised broadband matching network end of step 1. A bigger impedance transformation ratio is required for the input matching, compared with the output matching. As a result, a slightly better match can be obtained for the output matching-network, as shown in figure 9.37. The resulting element modification constants are shown in figure 9.38. It can be seen that some significant changes from the starting values have occurred. Figure 9.38. Element modification constants for figure 9.37. The second step in the amplifier design is to disable ports 2 and 4 and enable the FET subcircuit, as shown in figure 9.41. Enabling the amplifier activates the transfer impedances S21 and S12, causing significant changes in the frequency response. The circuit of figure 9.41, with the constants of figure 9.38 is then optimised, to obtain good matching for both the input and output. In the optimisation for S 11 and S 22 , the default goal L value must be disabled and L changed to 3, so that bigger errors have a much higher penalty. Figure 9.39 shows the resulting frequency response after this optimisation. RF Electronics: Design and Simulation 328 www.cadence.com/go/awr